Information-announcing system

ABSTRACT

An electronic announcing system for announcing the time at predetermined intervals, e.g., 10 seconds, wherein a digital clock is utilized with an audio storage drum in conjunction with a phase state or mode selector and control logic so that an audio readout is gated from the audio storage device every so often to announce the correct time.

United States Patent Inventors Gerald Goldschein [56] References Cited g f g Id uumao STATES PATENTS AP I No 21 3,237,171 2/1966 Young 340/1725 F A 23 1969 3,249,919 5/1966 Scantlin 179/6 x Patented 5 4 3,296,371 1/1967 Fox 179/1 Assignee cog'nimnics Corporation 3,300,591 1/1967 Gushue et a1. 179/100.3 Mount Kisco, NY. 3,409,895 11/1968 Hayden 346/ Continuation-impart of application Ser. No. FOREIGN PATENTS 730,730, May 21, 1968, now abando d, 257,856 8/1963 Australia 179/6 :1; :gg 1969 Primary Examiner-Bernard Konick Assistant Examiner-Raymond F. Cardillo, .Ir.

Attorney-Cushman, Darby & Cushman INFORMATION-ANNOUNCING SYSTEM 25 Claims Drawing Figs ABSTRACT: An electronic announcing system for announc- U.S. Cl 179/6 TA, ng h ime at pr e rmin in er l eg. 1 c n 179/100 C wherein a digital clock is utilized with an audio storage drum Int. Cl Gl1bl9/06, n j n i wi h a ph state r mode selector and centre! H04 1 /64 logic so that an audio readout is gated from the audio storage Field of Search 179/6 TA, 6 device ry so often to announce the correct time- CO, 100.2 Ml, 100.3 B, 100.1 C; 340/1725 z M/i/Vl/fl L 6 7 4 6406.4: 5'5 7" (/76. 9) w 2 1 7/0/V V $3 $54 mesg 06 5 r/ir' 0 I? C 0A! 7 04 M005 L 0 G/ C SEA-F670 PATENTEUJM 41912 31632.880

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SHEU 180F 29 

1. A system for announcing time comprising: means for storing a plurality of time information messages, means for determining the correct time and providing signals indicating the correct time, a plurality of gating means in circuit relationship with said storing means for each causing, when activated a different one of said messages on said storing means to be announced, and logic means in circuit relationship with said plurality of gating means and said determining means for receiving said time-indicating signals and for activating sequentially certain of said gating means determined at least in part by said timeindicating signals to cause a sequence of said messages to be announced so as to announce the correct time.
 2. The system of claim 1 further including: means in circuit relationship with said time-determining means for setting a time into said time-determining means.
 3. The system of claim 1 further including: means operatively associated with said time determining means for synchronizing said time-determining means to an external clock or synchronizing signal.
 4. The system of claim 3 wherein said synchronizing means includes: means for receiving said external clock or synchronizing signal; means operatively associated with said receiving means for operating on said clock signal; a plurality of gate means operatively associated with said time-determining means for synchronizing said time-determining means in accordance with said external clock signal; and means operatively associated with said operating means and with said plurality of gate means for gating said output from said operating means to said plurality of gate means.
 5. The system of claim 1 further indicating: means operatively associated with said time-determining means for providing the time in the form of a binary coded decimal signal at a binary coded decimal output.
 6. The system of claim 5 wherein said binary coded decimal output includes: first gate means operatively associated with said time-determining means for providing the time to the nearest 10 seconds; second gate means operatively associated with said time-determining means for providing the time to the nearest minute; third gate means operatively associated with said time-determining means for providing the time to the nearest 10 minutes; fourth gate means operatively associated with said time-determining means for providing the time to the nearest hour; and fifth gate means operatively associated with said time-determining means for providing the time to the nearest hour between 10 and
 20. 7. The system of claim 6 wherein said binary coded decimal output includes: sixth gate means operatively associated with said time-determining means for providing the time to the nearest hour between 20 and
 24. 8. The system of claim 1 in combination with a telephone system including a plurality of telephone lines wherein said announcing system includes: means in circuit relationship with said gating means for selectively coupling said announcing system to said telephone lines.
 9. The system of claim 8 wherein said coupling means includes: variable resistance means in circuit relationship with at least one of said telephone lines for changing resistance upon the occurrence of an AC ringing signal across said variable resistance means; first switching means; means in circuit with said variable resistance means and said first switching means for triggering said first switching means upon the changing of resistance of said variable resistance means; second switching means in circuit relationship with said first switching means; third switching means in circuit relationship with certain portions of said logic means for triggering from a first state to a second state when a predetermined mode has been selected by said mode selector means; and fourth switching means in circuit relationship with said second and third switching means and with said gating means wherein the activation of said fourth switching means electrically coupled said announcing system to said telephone system.
 10. The system of claim 9 wherein said coupling means further includes: counter means in circuit relationship with said portions of said logic means; and fifth switching means in circuit relationship with said counter means and said telephone lines for opening said lines following a predetermined number of time announcements from said announcing system.
 11. The system of claim 1 wherein said logic means includes: a plurality of flip-flops in circuit relationship with said coupling means, with one another and with said logic means wherein the output signals from said flip-flops relate to the mode of the system.
 12. The system of claim 11 wherein said logic means includes: a plurality of phase state NAND gates in circuit relationship with said flip-flops; a plurality of set NAND gates in circuit relationship with certain of said phase state NAND gates and with certain of said flip-flops; a plurality of reset NAND gates in circuit relationship with certain of said phase state NAND gates and with certain of said flip-flops; a plurality of time-representative NAND gates in circuit relationship with said time-determining means and said gating means; and wherein certain of said time-representative NAND gates are in circuit relationship with certain of said phase state NAND gates.
 13. The system of claim 12 wherein said gating means includes: a plurality of audio amplifiers in circuit relationship with certain of said phase state gates and certain of said time representative gates; and wherein said amplifiers have a common output.
 14. The system of claim 1 wherein said time-determining means includes: means for receiving an input signal of given frequency; and means in circuit with said receiving means for providing output signals of frequencies different from the frequency of said input signal.
 15. The system of claim 14 wherein said output signal providing means include: first counter means in circuit with said receiving meanS for providing an output signal at a fraction of the frequency of said input signal; second counter means in circuit with said first counter means for providing an output signal at a fraction of the frequency of the output signal from said first counter means; third counter means in circuit with said second counter means for providing an output signal at a fraction of the frequency of the output signal from said second counter means; fourth counter means in circuit with said third counter means for providing an output signal at a fraction of the frequency of the output signal from said third counter means; fifth counter means in circuit with said fourth counter means for providing an output signal at a fraction of the frequency of the output signal from said fourth counter means; sixth counter means in circuit with said fifth counter means for providing an output signal at a fraction of the frequency of the output signal from said fifth counter means; and seventh counter means in circuit with said sixth counter means for providing an output signal at a fraction of the frequency of the output signal from said sixth counter means.
 16. The system of claim 15 further including: eighth counter means in circuit with said seventh counter means for providing an output signal at a fraction of the frequency of the output signal from said seventh counter means.
 17. The system of claim 15 wherein each of said counter means includes a plurality of flip-flops in circuit relationship with one another.
 18. The system of claim 17 wherein said logic means is operatively associated with certain of said counter means to selectively enable the correct time to be read out by said system.
 19. The system of claim 18 wherein said logic means includes: a first plurality of NAND gates wherein each one is coupled to a predetermined number of said flip-flops in said fourth counter means; a second plurality of NAND gates wherein each one is coupled to a predetermined number of said flip-flops in said fifth counter means; a third plurality of NAND gates wherein each one is coupled to a predetermined number of said flip-flops in said sixth counter means; and a fourth plurality of NAND gates wherein each one is coupled to a predetermined number of said flip-flops in said seventh counter.
 20. The system of claim 19 wherein said logic means includes: means for coupling said logic means to said storing means; a plurality of phase state flip-flops in circuit relationship with said coupling means, with one another, and with said logic means wherein the output signals from said phase state flip-flops relate to the phase state or mode of the system.
 21. The system of claim 20 wherein said logic means further includes: a plurality of phase state NAND gates in circuit relationship with said phase state flip-flops and with certain of said pluralities of NAND gates that are coupled to said counter means; a plurality of set NAND gates in circuit relationship with certain of said phase state NAND gates and with certain of said phase state flip-flops; and a plurality of reset NAND gates in circuit relationship with certain of said phase state NAND gates and with certain of said phase state flip-flops.
 22. A system for announcing information comprising: means for storing a plurality of information messages, means for determining the correct information and providing signals indicating the correct information, a plurality of gating means in circuit relationship with said storing means for each causing, when activated, a different one of said messages on said storing means to be announced, and logic means in circuit relationship with said plurality of gating means and said determining means for receiving said information-indicating signals and for activating sequentially certain of said gating means determined at least in part of said information-indicating signals to cause a sEquence of said messages to be announced so as to announce the correct time.
 23. The system of claim 22 wherein said logic includes: means for coupling said logic to said storing means; and a plurality of flip-flops in circuit relations with said coupling means, with one another and with said logic means wherein the output signals from said flip-flops relate to the mode of the system.
 24. The system of claim 23 wherein said logic means includes: a plurality of phase state NAND gates in circuit relationship with said flip-flops; a plurality of set NAND gates in circuit relationship with certain of said phase state NAND gates and with certain said flip-flops; a plurality of reset NAND gates in circuit relationship with certain of said flip-flops; a plurality of information representative NAND gates in circuit relationship with said information-determining means and said gating means; and wherein certain of said last-mentioned NAND gates are in circuit relationship with certain of said phase state NAND gates.
 25. The system of claim 24 wherein said gating means includes: a plurality of audio amplifiers in circuit relationship with certain of said phase state gates and certain of said information representative gates; and wherein said amplifiers have a common output. 